1. Field of the Invention
The invention relates to integrated circuit decoders, and more particularly, to large scale integrated (LSI) circuit decoders which are configurable into different operating combinations and modes by means of applied control inputs.
2. Description of the Prior Art
As the state of the semiconductor art has advanced, the level of complexity of digital LSI circuits has greatly increased, and the cost per logic functions has concurrently decreased sharply. This has resulted in substantial economies to computer manufacturers. First, the initial cost of the LSI circuits has decreased. Second, the greatly increased level of functional complexity of LSI circuits has greatly reduced the number of integrated circuit packages which need to be interconnected, thereby increasing the reliability of the system and reducing costs of printed circuit boards on which the integrated circuit packages are mounted.
Although certain sections of a typical computer, such as the main memory, the arithmetic and logic unit, and the firmware memory may be implemented utilizing commercially available "standard" LSI circuits such as random access memory circuits, read only memories, and arithmetic circuits, other sections (which are referred to herein as "random logic sections") of computers are not readily implementable with such standard parts. The random logic sections include various interconnections of logic circuits which are peculiar to a particular computer design. For the random logic sections of a computer, it may be difficult for computer designers to take full advantage of the potential economies generally associated with standard LSI circuits (which are produced in great volumes and consequently have low cost per function). This is because the random logic sections must usually be implemented by "custom designed" LSI circuits or by medium scale integrated (MSI) circuits having much lower functional density per semiconductor chip. High engineering costs are ordinarily incurred in the development of custom designed LSI circuits; consequently, the relatively low volumes of custom designed LSI circuits used for a particular computer prevent the economies usually associated with LSI circuits from being realized for the random logic section of a computer. Thus, there is a great need to reduce the number of different types of LSI circuits which must be utilized in implementing the random logic portion of a digital computer so that the potential economies of large scale integrated circuit technology can be exploited for the random logic section of a computer.
Decoding circuits of various types are utilized in large numbers in a typical computer. However, such decoding circuits perform a wide variety of specialized functions. Therefore, use of standard LSI circuits for such decoding circuits is impractical, since a large number of specialized custom designed LSI decoding circuits would be required. The production volumes for each custom designed decoding circuit would be very low, and the cost per decoding function would be very high because of the high engineering costs associated with development of each different custom designed LSI decoding circuit.
When a decoding function requiring a large number of input variables and a large number of outputs is required, a number of "smaller" decoders (wherein each of the smaller decoders has fewer inputs and fewer outputs than the subject decoding function) are ordinarily utilized. Interconnection of such "smaller" decoders to obtain "larger" decoders ordinarily involves use of additional logic gates. This results in addition of "gate delays" (associated with such additional logic gates) to the total decoder delay, thereby reducing speed of operation of the "larger" decoder. There is clearly a need for new techniques and new circuits to permit the computer designer to provide circuits which produce the various decoding function required in a typical computer and still achieve the economies typically achievable by use of high volume LSI circuits.